The present invention relates to a position detecting method suitable for alignment between a reticle and a wafer for use with an exposure apparatus that exposes an object, such as a single crystal substrate for a semiconductor wafer, and a glass plate for a liquid crystal display (“LCD”).
Projection exposure apparatuses used to manufacture semiconductor devices, such as ICs, LSIs, and VLSIs, have been required to expose a circuit pattern on a reticle onto a wafer with high resolution along with demands for finer and higher density circuits. The projection resolving power of a circuit pattern depends upon a numerical aperture (“NA”) of a projection optical system and a wavelength of exposure light, and methods to achieve high resolution include a method to increase an NA of a projection optical system and a method to use exposure light having a shorter wavelength. Regarding the latter method, an exposure light source has shifted from g-line to i-line and from i-line to the excimer laser. Exposure apparatuses that use the excimer laser having an oscillation wavelength of 248 nm and 193 nm have already been reduced to practice.
At present, those exposure methods have been currently studied for the next generation, which use a vacuum ultraviolet (“VUV”) exposure method that uses exposure light having a wavelength of 157 nm and an extreme ultraviolet (“EUV”) exposure method that uses exposure light having a wavelength of around 13 nm.
Manufacture processes of semiconductor devices are diversified, and the planation technology for solving a problematically small depth of focus in an exposure apparatus have called attention, such as a Tungsten Chemical Mechanical Polishing (“W-CMP”) process, Cu dual damocene wiring technology, and technology that applies a low dielectric constant (“Low-k”) material to an interlayer dielectric. There have been proposed a wide variety of structures and materials for semiconductor devices, for example, Pseudomorphic High Electron Mobility Transistor (“P-HEMT”) and Metamorphe-HEMT (“M-HEMT”) made of compound such as GaAs and InP, Heterojunction Bipolar Transistors (“HBTs”) that use SiGe, SiGeC, etc.
On the other hand, fine circuit patterns have required a precise alignment between a reticle (mask) that forms a circuit pattern and a wafer to which the circuit pattern is projected; the necessary precision is about ⅓ of a circuit critical dimension, e.g., 60 nm that is ⅓ as long as the current design width of 180 nm.
Alignment in an exposure apparatus usually images an optical image of an alignment mark formed on a wafer, onto an image pickup device, such as a CCD camera, and image-processes an electric signal to detect a position of the mark on the wafer.
In general, a non-uniform film thickness of resist near the alignment mark and an asymmetric shape of the alignment mark are influential factors that deteriorate alignment accuracy on the wafer upon alignment between the reticle and wafer. These alignment error factors caused by the wafer are referred to as wafer induced shift (“WIS”).
It is a vital issue to improve the overlay accuracy for actual wafer device as one of three factors in an exposure apparatus for improved performance of semiconductor devices and manufacture yield. However, an introduction of special semiconductor manufacturing technology, such as a CMP process, has problematically generated defects in alignment marks although a circuit pattern has a good structure. This is caused by a large difference in critical dimension between a circuit pattern and an alignment mark along with a fine circuit pattern. In other words, it appears that this problem occurs since process conditions, such as a film formation, etching, and CMP, are optimized for a fine circuit pattern (with a critical dimension from 0.1 to 0.15 μm) but not for a large alignment mark (with a critical dimension from 0.6 to 4.0 μm).
When a critical dimension of an alignment mark is attempted to fit that of a circuit pattern, a microscope used for the alignment comes to have insufficient resolution, and signal intensity or contrast reduces, deteriorating stability of a detected signal of an alignment mark. A detection optical system that may detect an alignment mark that has a critical dimension equivalent to that of the circuit pattern requires a high NA and a light source having a short wavelength for alignment, i.e., an optical system having performance as high as that of a projection optical system for transferring a circuit pattern, generating another problem of increased apparatus cost.
At present, when this problem occurs, a process condition is changed by trial and error, for example, by resetting the condition suitable for both the alignment mark and circuit pattern, or by manufacturing plural types of alignment marks having different critical dimensions, by evaluating the exposure results, and by using such an alignment mark as has the best critical dimension.
Therefore, it takes a long time to determine the best condition or parameters. In addition, even after parameters are determined, the parameters should be changed, when a wafer process error WIS occurs, for an exposure apparatus along with a changing manufacture process. This also requires a long time. In addition, it is expected in the future that it will be increasingly difficult to manufacture both a circuit pattern and an alignment mark on a whole wafer surface without defect due to more demands of finer circuit patterns, an introduction of new semiconductor processes, and a large wafer diameter up to 300 mm.
FIG. 5 shows a conventional exemplary detected signal of an alignment mark. As shown in FIG. 5A, an approach has been generally known which detects edges of a mark so as to detect a mark position from a raw signal as a result of detections of plural alignment marks (or mark raw signal).
The edge detection is an approach for calculating a maximum or minimum position of primary differentiation to the mark raw signal shown in FIG. 5A, but this approach is subject to influence of high-frequency noises when a raw signal from a sensor is primarily differentiated. Accordingly, some pretreatment or filtering is needed. More specifically, as shown in FIG. 5C, for example, it is conceivable to carry out the primary differentiation after a zero phase filtering. Here, the “zero phase filtering” is defined as a process to invert and re-filter a data string filtered according to forward filtering. Therefore, the data string obtained from the zero phase filtering has a phase distortion of strictly zero, providing permanent phase information shown in FIG. 5 in an abscissa axis on a paper surface.
There is no definite criterion to determine how much parameter or order the zero phase filtering has. Under the present conditions, the best parameter or order is determined, for example, by using a method of comparing a mark raw signal with a filtered signal at a waveform level and minimizing a sum of squares in a residual error, a method of comparing these frequency characteristics and confirming whether the high-frequency noise component has been removed, etc.
When a mark raw signal includes an error due to influence of a wafer process error WIS, etc., the filtered signal includes a distortion component, whereby the WIS affects the edge detection, and finally a detection of a mark position.